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Integrated interlayer via planning and pin assignment for 3D ICs., , , and . SLIP, page 99-104. ACM, (2009)Stairway compaction using corner block list and its applications with rectilinear blocks., , , , , and . ACM Trans. Design Autom. Electr. Syst., 9 (2): 199-211 (2004)Effective congestion reduction for IC package substrate routing., , , , , and . ACM Trans. Design Autom. Electr. Syst., 15 (3): 27:1-27:21 (2010)Topological routing to maximize routability for package substrate., , , , , , and . DAC, page 566-569. ACM, (2008)Simultaneous slack budgeting and retiming for synchronous circuits optimization., , , and . ASP-DAC, page 49-54. IEEE, (2010)PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization., , , , and . ASP-DAC, page 769-774. IEEE, (2010)Reliable buffered clock tree routing algorithm with process variation tolerance., , , and . Sci. China Ser. F Inf. Sci., 48 (5): 670-680 (2005)A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior., , , and . Sci. China Ser. F Inf. Sci., 45 (4): 310-320 (2002)Power/Ground Network Optimization Considering Decap Leakage Currents., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (10): 1012-1016 (2006)A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (10): 1007-1011 (2006)