( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.

, , , , , , , , , , , , и . VLSI Circuits, стр. 120-. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Jia Chen

Jia Chen

Jing Chen

Jing Chen

Jing Chen

 

Другие публикации лиц с тем же именем

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface., , , , , , и . A-SSCC, стр. 73-76. IEEE, (2014)Parallelizing SRAM arrays with customized bit-cell for binary neural networks., , , , , , , , и . DAC, стр. 21:1-21:6. ACM, (2018)A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS., , , , , , , , , и 3 other автор(ы). VLSI Circuits, стр. 120-. IEEE, (2019)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors., , , , , , , , , и 6 other автор(ы). A-SSCC, стр. 217-218. IEEE, (2019)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 496-498. IEEE, (2018)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 396-398. IEEE, (2019)