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Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique.

, , , и . SoCC, стр. 215-220. IEEE, (2015)

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Hans Madsen

Henning Madsen

Hans Madsen

Hans Madsen

Hans Madsen

 

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Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique., , , и . SoCC, стр. 215-220. IEEE, (2015)Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching., , , и . ICCD, стр. 463-468. IEEE Computer Society, (2017)Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology., , , , , , и . ICCD, стр. 326-331. IEEE Computer Society, (2011)Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective., , , и . SoCC, стр. 449-454. IEEE, (2014)Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications., , , и . ESSDERC, стр. 172-175. IEEE, (2017)Robust subthreshold 7T-SRAM cell for low-power applications., и . MWSCAS, стр. 893-896. IEEE, (2014)8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology., , , и . VLSI-SoC (Selected Papers), том 464 из IFIP Advances in Information and Communication Technology, стр. 95-109. Springer, (2014)Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power., , , и . ISVLSI, стр. 74-79. IEEE Computer Society, (2015)Flip-flop design using novel pulse generation technique., , , и . ICECS, стр. 685-688. IEEE, (2012)Spin-Orbit-Torque-based Devices, Circuits and Architectures., , , , , , , , , и 2 other автор(ы). CoRR, (2019)