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Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective.

, , , and . SoCC, page 449-454. IEEE, (2014)

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Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching., , , and . ICCD, page 463-468. IEEE Computer Society, (2017)Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique., , , and . SoCC, page 215-220. IEEE, (2015)Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective., , , and . SoCC, page 449-454. IEEE, (2014)Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications., , , and . ESSDERC, page 172-175. IEEE, (2017)Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology., , , , , , and . ICCD, page 326-331. IEEE Computer Society, (2011)8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology., , , and . VLSI-SoC (Selected Papers), volume 464 of IFIP Advances in Information and Communication Technology, page 95-109. Springer, (2014)Robust subthreshold 7T-SRAM cell for low-power applications., and . MWSCAS, page 893-896. IEEE, (2014)Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power., , , and . ISVLSI, page 74-79. IEEE Computer Society, (2015)Flip-flop design using novel pulse generation technique., , , and . ICECS, page 685-688. IEEE, (2012)Low-power comparator in 65-nm CMOS with reduced delay time., , , and . ICECS, page 736-739. IEEE, (2016)