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A high-speed, low-power 3D-SRAM architecture., , and . CICC, page 201-204. IEEE, (2008)A Verilog piecewise-linear analog behavior model for mixed-signal validation., and . CICC, page 1-5. IEEE, (2013)Digital Analog Design: Enabling Mixed-Signal System Validation., , , , and . IEEE Des. Test, 32 (1): 44-52 (2015)Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models., and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 23-33 (2016)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)Energy-Performance Tunable Logic., , and . IEEE J. Solid State Circuits, 44 (9): 2554-2567 (2009)CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography., , , , and . IEEE J. Solid State Circuits, 47 (4): 1031-1042 (2012)TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators., , , , and . ASPLOS, page 807-820. ACM, (2019)False coupling exploration in timing analysis., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1795-1805 (2005)Timing analysis including clock skew., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (11): 1608-1618 (1999)