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Disambiguation of "Sakanushi, Keishi"

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An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost.

, , , and . ASP-DAC, page 338-341. ACM, (2003)

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Electronic triage system for continuously monitoring casualties at disaster scenes., , , , , , , and . J. Ambient Intell. Humaniz. Comput., 4 (5): 547-558 (2013)Recognition of Floorplan by Parametric BSG for Reuse of Layout Design., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (4): 872-879 (2002)Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors., , , , , , and . ASP-DAC, page 449-454. IEEE, (2009)Enabling RTOS simulation modeling in a system level design language., , , and . ASP-DAC, page 936-939. ACM Press, (2005)A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units., , , , and . ASP-DAC, page 286-291. IEEE Computer Society, (2007)RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC., , , and . DATE, page 554-559. IEEE Computer Society, (2005)Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation., , , , and . ICDCS Workshops, page 824-830. IEEE Computer Society, (2004)Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures., , , , and . VLSI-SoC, page 290-295. IEEE, (2006)Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model., , , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 357-376. Springer, (2006)Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2800-2809 (2007)