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Variation-Aware, Library Compatible Delay Modeling Strategy., , , and . VLSI-SoC, page 122-127. IEEE, (2006)Positive realization of reduced RLCM nets., and . VLSI-SoC, page 398-403. IEEE, (2011)Efficient analysis of variability impact on interconnect lines and resistor networks., and . DATE, page 1-6. European Design and Automation Association, (2014)Black-box model reduction of the C. Elegans nervous system*., and . EMBC, page 4174-4179. IEEE, (2021)On Generating Compact, Passive Models of Frequency-Described Systems., , and . SBCCI, page 302-307. IEEE Computer Society, (2002)Improving the efficiency of parasitic extraction and simulation of 3D interconnect models., , , and . ICECS, page 1729-1732. IEEE, (1999)A probabilistic approach for RT-level power modeling., , , and . ICECS, page 911-914. IEEE, (1999)On the Effectiveness of Reducing Large Linear Networks with Many Ports., and . ISCAS, page 2694-2697. IEEE, (2007)Parametric Structure-Preserving Model Order Reduction., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-20. Springer, (2007)Techniques for Brain Functional Connectivity Analysis from High Resolution Imaging., , , , , , , , and . CompleNet, volume 597 of Studies in Computational Intelligence, page 131-138. Springer, (2015)