Author of the publication

Model-Based Processor-in-the-Loop Framework for Composable Multi-core Platforms.

, , , and . DSD, page 592-596. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Component-Level ASIL Decomposition for Automotive Architectures., , and . DSN Workshops, page 62-69. IEEE, (2019)Hybrid Timeslot Design for IEEE 802.15.4 TSCH to Support Heterogeneous WSNs., , , and . PIMRC, page 1-7. IEEE, (2018)A distributed architecture to check global properties for post-silicon debug., , and . European Test Symposium, page 182-187. IEEE Computer Society, (2010)A reconfigurable real-time SDRAM controller for mixed time-criticality systems., , , and . CODES+ISSS, page 2:1-2:10. IEEE, (2013)Deadlock Prevention in the Æthereal Protocol., , , , , and . CHARME, volume 3725 of Lecture Notes in Computer Science, page 345-348. Springer, (2005)A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control., , , , and . CODES+ISSS, page 130-135. ACM, (2006)An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 4-17 (2005)Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms., , , , and . Map2MPSoC/SCOPES, page 13-21. ACM, (2012)Dependable Interference-Aware Time-Slotted Channel Hopping for Wireless Sensor Networks., , , and . ACM Trans. Sens. Networks, 14 (1): 3:1-3:35 (2018)Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes., , and . CoRR, (2020)