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Disambiguation of "Hofstee, H. Peter"

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A 690 ps read-access latency register file for a GHz integer microprocessor.

, , , , and . ICCD, page 6-10. IEEE Computer Society, (1998)

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Peter H Kunerth

Peter H Kornicker

H Peter Rodemann

Peter H Werhahn

Peter H Krämer

 

Other publications of authors with the same name

Invited speakers II - Real-time supercomputing and technology for games and entertainment.. SC, page 199. ACM Press, (2006)Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow., , , , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 32-47. Springer, (2019)SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs., , , , , , , and . IPDPS, page 728-738. IEEE, (2022)Distributing a Class of Sequential Programs.. MPC, volume 669 of Lecture Notes in Computer Science, page 139-162. Springer, (1992)Tydi-lang: A Language for Typed Streaming Hardware., , , , , , and . SC Workshops, page 520-529. ACM, (2023)A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress., , , , and . CODES+ISSS, page 16. IEEE / ACM, (2018)High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor., , , , , , and . VTS, page 234-238. IEEE Computer Society, (1998)Understanding system design for Big Data workloads., , , , , , , , , and . IBM J. Res. Dev., 57 (3/4): 3 (2013)Introduction to the Cell multiprocessor., , , , , and . IBM J. Res. Dev., 49 (4-5): 589-604 (2005)NASB: Neural Architecture Search for Binary Convolutional Neural Networks., , and . IJCNN, page 1-8. IEEE, (2020)