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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

M. Clinton, H. Cheng, H. Liao, R. Lee, C. Wu, J. Yang, H. Hsieh, F. Wu, J. Yang, A. Katoch, A. Achyuthan, D. Mikan, B. Sheffield, and J. Chang. ISSCC, page 210-211. IEEE, (2017)

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Jonathan

Fu-Chang Chang

Sheng-Chia Chang

William Ockham's view on human capabilityS. Chang. Uni Frankfurt Main, (2009)

Jonathan Tolson

Jonathan Burmeister

Other publications of authors with the same name

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.J. Chang, Y. Chen, W. Chan, S. Singh, H. Cheng, H. Fujiwara, J. Lin, K. Lin, J. Hung, R. Lee and 6 other author(s). ISSCC, page 206-207. IEEE, (2017)A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.M. Clinton, R. Singh, M. Tsai, S. Zhang, B. Sheffield, and J. Chang. ISSCC, page 200-201. IEEE, (2018)Electromigration failure rate of redundant via.J. Ahn, P. Yeh, and J. Chang. IRPS, page 1. IEEE, (2018)Product-level reliability estimator with budget-based reliability management in 20nm technology.J. Ahn, M. Lu, N. Navale, D. Graves, P. Yeh, J. Chang, and S. Pai. IRPS, page 6. IEEE, (2015)SE1: What Technologies Will Shape the Future of Computing?H. Mair, S. Shiratake, E. Karl, T. Burd, J. Chang, D. Marr, S. Naffziger, H. Corporaal, K. Takeuchi, and N. Shanbhag. ISSCC, page 537-538. IEEE, (2021)Gesture Recognition in the Haptic Creature.J. Chang, K. MacLean, and S. Yohanan. EuroHaptics (1), volume 6191 of Lecture Notes in Computer Science, page 385-391. Springer, (2010)Location3: How Users Share and Respond to Location-Based Data on Social.J. Chang, and E. Sun. ICWSM, The AAAI Press, (2011)Estimation of Product Reliability using TDDB Simulation and Statistical EM Method.J. Ahn, P. Yeh, and J. Chang. IRPS, page 1-6. IEEE, (2020)FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems.Y. Chiang, W. Chien, Y. Chih, J. Chang, C. Lin, and Y. King. Integr., (2019)A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.M. Sinangil, B. Erbagci, R. Naous, K. Akarvardar, D. Sun, W. Khwa, H. Liao, Y. Wang, and J. Chang. IEEE J. Solid State Circuits, 56 (1): 188-198 (2021)

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Disambiguation of "Chang, Jonathan"

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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

Please choose a person to relate this publication to

Jonathan

Fu-Chang Chang

Sheng-Chia Chang

Jonathan Tolson

Jonathan Burmeister

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chang, Jonathan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

Please choose a person to relate this publication to

Jonathan

Fu-Chang Chang

Sheng-Chia Chang

Jonathan Tolson

Jonathan Burmeister

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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Chicago
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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.