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Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX.

, , , and . USENIX Security Symposium, page 51-67. USENIX Association, (2017)

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Exploring the Potential of Architecture-Level Power Optimizations., and . PACS, volume 3164 of Lecture Notes in Computer Science, page 132-147. Springer, (2003)Introduction., and . ACM Trans. Archit. Code Optim., 2 (1): 1-2 (2005)Editorial: Special Section on CMP Architectures., and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1025-1027 (2007)Heterogeneous Computing Guest editors' introduction., and . IEEE Micro, 35 (4): 4-5 (2015)Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management., , and . IEEE Micro, 39 (3): 75-83 (2019)Symbiotic jobscheduling for a simultaneous multithreaded processor, and . SIGARCH Comput. Archit. News, 28 (5): 234--244 (November 2000)Fast switching of threads between cores., , , , and . ACM SIGOPS Oper. Syst. Rev., 43 (2): 35-45 (2009)Mitigating Speculative Execution Attacks via Context-Sensitive Fencing., , and . IEEE Des. Test, 39 (4): 49-57 (2022)Hardware Identification of Cache Conflict Misses., and . MICRO, page 126-135. ACM/IEEE Computer Society, (1999)The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU., and . MICRO, page 281-293. ACM, (2015)