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Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX.

, , , и . USENIX Security Symposium, стр. 51-67. USENIX Association, (2017)

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Julien DeAntoni

Graham Deane

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Dean Spinanger

 

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Exploring the Potential of Architecture-Level Power Optimizations., и . PACS, том 3164 из Lecture Notes in Computer Science, стр. 132-147. Springer, (2003)Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy., , , и . MICRO, стр. 183-194. IEEE Computer Society, (2004)Control Flow Optimization Via Dynamic Reconvergence Prediction., , и . MICRO, стр. 129-140. IEEE Computer Society, (2004)Reducing power with dynamic critical path information., , и . MICRO, стр. 114-123. ACM/IEEE Computer Society, (2001)Pointer cache assisted prefetching., , , и . MICRO, стр. 62-73. ACM/IEEE Computer Society, (2002)The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU., и . MICRO, стр. 281-293. ACM, (2015)Hardware Identification of Cache Conflict Misses., и . MICRO, стр. 126-135. ACM/IEEE Computer Society, (1999)Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures., , и . PMAM@PPoPP, стр. 51-60. ACM, (2019)Multithreaded Value Prediction., и . HPCA, стр. 5-15. IEEE Computer Society, (2005)A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework., , и . CGO, стр. 50-64. IEEE Computer Society, (2006)