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A timing-accurate modeling and simulation environment for networked embedded systems., , , , , and . DAC, page 42-47. ACM, (2003)Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints., , and . DAC, page 110:1-110:6. ACM, (2013)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)Low-energy for deep-submicron address buses., , and . ISLPED, page 176-181. ACM, (2001)Using soft-edge flip-flops to compensate NBTI-induced delay degradation., , and . ACM Great Lakes Symposium on VLSI, page 169-172. ACM, (2009)Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip., , and . ISCAS (2), page 361-364. IEEE, (2004)A hierarchical multi-level test generation system., and . Great Lakes Symposium on VLSI, page 54-59. IEEE, (1991)Pass-XNOR logic: A new logic style for P-N junction based graphene circuits., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control., , and . DAC, page 22-27. ACM Press, (1997)Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms., , , , and . DAC, page 247-252. ACM Press, (1999)