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D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems.

, , , , and . ReCoSoC, page 1-6. IEEE, (2013)

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On the automatic integration of hardware accelerators into FPGA-based embedded systems., , , , , and . FPL, page 607-610. IEEE, (2012)Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 14 (3): 15:1-15:33 (2021)Automated Fine-Grained CPU Provisioning for Virtual Machines., , , and . ACM Trans. Archit. Code Optim., 11 (3): 27:1-27:25 (2014)Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA., , , , , , and . ICSAMOS, page 107-114. IEEE, (2006)Towards a performance-as-a-service cloud., , , , , and . SoCC, page 26:1-26:2. ACM, (2013)A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication., , , , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 232-250. Springer, (2008)Exploring transductive and inductive methods for vertex embedding in biological networks., , , and . RTSI, page 285-290. IEEE, (2019)Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign., and . FPL, page 1-2. IEEE, (2006)A Case Study for an Accelerated DCNN on FPGA-Based Embedded Distributed System., , , , and . IPDPS Workshops, page 91-94. IEEE, (2019)Operating system support for online partial dynamic reconfiguration management., , and . FPL, page 455-458. IEEE, (2008)