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A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications.

, , , , and . ISCAS, page 1-5. IEEE, (2024)

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Phase-Encoding for On-Chip Signalling., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (2): 535-545 (2008)Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip., , , , , , , , and . ARITH, page 37-44. IEEE, (2018)Design of High-Performance while Energy-Efficient Microprocessor with Novel Asynchronous Techniques: (PhD Forum Paper)., and . ASAP, page 247-248. IEEE, (2024)Variability analysis of self-timed SRAM robustness., , , and . PATMOS, page 24-31. IEEE, (2013)Multiple-Rail Phase-Encoding for NoC., , , , and . ASYNC, page 107-116. IEEE Computer Society, (2006)PSK Signalling on NoC Buses., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 286-296. Springer, (2005)Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path., , , and . NEWCAS, page 1-4. IEEE, (2016)ORSAS: An Output Row-Stationary Accelerator for Sparse Neural Networks., , and . IEEE Access, (2023)Multiscale Residual Network with Dynamic Depthwise Convolution for Multi-label 12-Lead ECG Classification., , and . IJCNN, page 1-8. IEEE, (2024)Differentiable architecture search with multi-dimensional attention for spiking neural networks., , , , and . CoRR, (2024)