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A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.

, , , , и . DATE, стр. 247-252. IEEE Computer Society, (2004)

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Georgios Galanis

Michalis Titsias

Michalis Christofi

Michalis Kapsos

Georgios Michalis

 

Другие публикации лиц с тем же именем

High-speed hardware implementations of the KASUMI block cipher., , и . ISCAS (2), стр. 549-552. IEEE, (2004)A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms., , , , и . DATE, стр. 247-252. IEEE Computer Society, (2004)A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher., , и . ISCAS (5), стр. 4641-4644. IEEE, (2005)A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures., , и . IPDPS, IEEE Computer Society, (2005)A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels., , , и . Journal of Circuits, Systems, and Computers, 14 (4): 877-893 (2005)Mapping DSP applications on processor/coarse-grain reconfigurable array architectures., , и . ISCAS, IEEE, (2006)Resource constrained modulo scheduling for coarse-grained reconfigurable arrays., , и . ISCAS, IEEE, (2006)A Novel Data-Path for Accelerating DSP Kernels., , , , и . SAMOS, том 3133 из Lecture Notes in Computer Science, стр. 363-372. Springer, (2004)Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware., , и . IPDPS, IEEE, (2006)A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard., , , и . ISCAS (1), стр. 472-475. IEEE, (2005)