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A 32nm 0.5V-supply dual-read 6T SRAM.

, , , , , , , , , , , , , , и . CICC, стр. 1-4. IEEE, (2010)

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Ludwig Sautter

Peter Sautter

Dieter Sautter

Fritz Sautter

Theodor Sautter

 

Другие публикации лиц с тем же именем

The vector fixed point unit of the synergistic processor element of the cell architecture processor., , , , , , и . ESSCIRC, стр. 203-206. IEEE, (2005)A 32nm 0.5V-supply dual-read 6T SRAM., , , , , , , , , и 5 other автор(ы). CICC, стр. 1-4. IEEE, (2010)A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology., , , , , , , , , и 4 other автор(ы). ESSCIRC, стр. 303-307. IEEE, (2017)A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction., , , , , , , и . ESSCIRC, стр. 343-346. IEEE, (2015)The vector fixed point unit of the synergistic processor element of the cell architecture processor., , , , , , и . DATE Designers' Forum, стр. 244-248. European Design and Automation Association, Leuven, Belgium, (2006)A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 344-345. IEEE, (2010)