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Disambiguation of "Shimoda, Masayuki"

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A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA.

, , , and . FPT, page 267-270. IEEE, (2019)

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Masayuki Hirosue

Jun Shimoda

Masayuki Maenishi

Masayuki Yamamoto

Masayuki Inaba

 

Other publications of authors with the same name

Fast Monocular Depth Estimation on an FPGA., , , , , and . IPDPS Workshops, page 143-146. IEEE, (2020)Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs., , and . FPL, page 461-462. IEEE Computer Society, (2018)Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation., , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 371-386. Springer, (2019)A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector., , and . FPT, page 298-301. IEEE, (2018)Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA., , and . IEICE Trans. Inf. Syst., 102-D (5): 1020-1028 (2019)Power Efficient Object Detector with an Event-Driven Camera on an FPGA., , and . HEART, page 10:1-10:6. ACM, (2018)Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks., and . ECOC, page 1-4. IEEE, (2021)Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning., and . ECOC, page 1-4. IEEE, (2021)A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA., , , and . FPT, page 267-270. IEEE, (2019)FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network., , , , , and . FPL, page 180-186. IEEE, (2019)