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A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop., , , , , , , and . CICC, page 81-84. IEEE, (2003)CMOS circuits for Gb/s serial data communication., , , , , and . IBM J. Res. Dev., 39 (1-2): 73-82 (1995)A 5.2 GHz 3.3 V I/Q SiGe RF transceiver., , and . CICC, page 217-220. IEEE, (1999)Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICs., , , , , , , , , and 7 other author(s). CICC, page 559-566. IEEE, (2001)Integrated RF components in a SiGe bipolar technology., , , , , , , and . IEEE J. Solid State Circuits, 32 (9): 1440-1445 (1997)A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery., , and . ISCAS, page 187-190. IEEE, (1995)A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links., , , , , , , , , and 14 other author(s). VLSI Technology and Circuits, page 28-29. IEEE, (2022)An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS., , , , , , , , , and 17 other author(s). VLSI Technology and Circuits, page 168-169. IEEE, (2022)