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A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.

W. Rhee, H. Ainspan, S. Rylov, A. Rylyakov, M. Beakes, D. Friedman, S. Gowda, and M. Soyuer. CICC, page 81-84. IEEE, (2003)

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Andreas Herschel

Olga Herschel

Wilhelm Herschel

Knut Herschel

Daniela Herschel

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Experimental Analysis of Substrate Noise Effect on PLL Performance.W. Rhee, K. Jenkins, J. Liobe, and H. Ainspan. IEEE Trans. Circuits Syst. II Express Briefs, 55-II (7): 638-642 (2008)CMOS circuits for Gb/s serial data communication.J. Ewen, M. Soyuer, A. Widmer, K. Wrenner, B. Parker, and H. Ainspan. IBM J. Res. Dev., 39 (1-2): 73-82 (1995)Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements.F. Stellari, P. Song, and H. Ainspan. VTS, page 1-6. IEEE Computer Society, (2014)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.T. Dickson, Y. Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, and D. Friedman. CICC, page 1-4. IEEE, (2015)A 5.2 GHz 3.3 V I/Q SiGe RF transceiver.J. Plouchart, H. Ainspan, and M. Soyuer. CICC, page 217-220. IEEE, (1999)FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.B. Lee, N. Dupuis, J. Orcutt, J. Ayala, K. Nummy, H. Ainspan, J. Proesel, C. Baks, D. Gill, M. Meghelli and 1 other author(s). OFC, page 1-3. IEEE, (2018)A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.B. Sadhu, A. Valdes-Garcia, J. Plouchart, H. Ainspan, A. Gupta, M. Ferriss, M. Yeck, M. Sanduleanu, X. Gu, C. Baks and 2 other author(s). IEEE J. Solid State Circuits, 55 (6): 1516-1529 (2020)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.A. Rylyakov, J. Tierno, H. Ainspan, J. Plouchart, J. Bulzacchelli, Z. Deniz, and D. Friedman. ISSCC, page 94-95. IEEE, (2009)TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.D. Bhattacharya, R. Joshi, H. Ainspan, N. Sathaye, M. Bajaj, S. Gundapaneni, and N. Jha. CICC, page 1-4. IEEE, (2014)Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.T. Dickson, Z. Deniz, M. Cochet, J. Bulzacchelli, M. Kossel, P. Francese, T. Morf, J. Proesel, H. Ainspan, M. Brändli and 1 other author(s). CICC, page 1-8. IEEE, (2024)

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Disambiguation of "Ainspan, Herschel A."

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A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.

Please choose a person to relate this publication to

Andreas Herschel

Olga Herschel

Wilhelm Herschel

Knut Herschel

Daniela Herschel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ainspan, Herschel A."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.

Please choose a person to relate this publication to

Andreas Herschel

Olga Herschel

Wilhelm Herschel

Knut Herschel

Daniela Herschel

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.