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Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS., , , and . VLSI Technology and Circuits, page 68-69. IEEE, (2022)An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS., , , and . IEEE J. Solid State Circuits, 58 (4): 1117-1128 (2023)microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware., , , , , and . ESSCIRC, page 421-424. IEEE, (2023)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI., , , , , , , , , and 6 other author(s). FPGA, page 119. ACM, (2019)A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS., , , , and . VLSI Circuits, page 255-256. IEEE, (2018)25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range., , , , , , , , , and 4 other author(s). ISSCC, page 396-398. IEEE, (2020)Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs., , , , , , , , , and 6 other author(s). FCCM, page 199-207. IEEE, (2019)A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)