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Disambiguation of "Seshadri, Vivek"

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ChargeCache: Reducing DRAM latency by exploiting row access locality.

, , , , , , and . HPCA, page 581-593. IEEE Computer Society, (2016)

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Praveen Seshadri

Sangeetha Seshadri

Varadarajan Seshadri

Nagarajavel Vivekananthan

Vivek Venkataramani

 

Other publications of authors with the same name

RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization., , , , , , , , , and 1 other author(s). MICRO, page 185-197. ACM, (2013)Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology., , , , , , , , , and . MICRO, page 273-287. ACM, (2017)PARIKSHA : A Large-Scale Investigation of Human-LLM Evaluator Agreement on Multilingual and Multi-Cultural Data., , , , , and . CoRR, (2024)BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3071-3087 (2016)Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks., , , , , , and . ACM Trans. Archit. Code Optim., 11 (4): 51:1-51:22 (2014)Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses., , , , , , and . MICRO, page 267-280. ACM, (2015)Crowdsourcing Speech Data for Low-Resource Languages from Low-Income Workers., , , , , , , , , and . LREC, page 2819-2826. European Language Resources Association, (2020)MISE: Providing performance predictability and improving fairness in shared main memory systems., , , , and . HPCA, page 639-650. IEEE Computer Society, (2013)Adaptive-latency DRAM: Optimizing DRAM timing for the common-case., , , , , , and . HPCA, page 489-501. IEEE Computer Society, (2015)ChargeCache: Reducing DRAM latency by exploiting row access locality., , , , , , and . HPCA, page 581-593. IEEE Computer Society, (2016)