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Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform., , , и . IEEE Access, (2022)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1178-1191 (2021)Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion., и . DAC, стр. 214-219. ACM Press, (1997)Improved Channel Routing by Via Minimization and Shifting., и . DAC, стр. 677-680. ACM, (1988)An Efficient Timing-Driven Global Routing Algorithm., , , и . DAC, стр. 596-600. ACM Press, (1993)Predicting the worst-case voltage violation in a 3D power network., , , , , и . SLIP, стр. 93-98. ACM, (2009)Worst-case performance prediction under supply voltage and temperature variation., , , и . SLIP, стр. 91-96. ACM, (2010)Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing., , , , и . SLIP, стр. 71-76. ACM, (2003)Placement and beyond in honor of Ernest S. Kuh.. ISPD, стр. 5-8. ACM, (2011)Stairway compaction using corner block list and its applications with rectilinear blocks., , , , , и . ACM Trans. Design Autom. Electr. Syst., 9 (2): 199-211 (2004)