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Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures.

, , , and . MICRO, page 237-246. ACM/IEEE Computer Society, (1998)

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Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . Int. J. Parallel Program., 32 (6): 447-474 (2004)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)Register Constrained Modulo Scheduling., , , and . IEEE Trans. Parallel Distributed Syst., 15 (5): 417-430 (2004)A comparative study of modulo scheduling techniques., , and . ICS, page 97-106. ACM, (2002)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Optimizing Program Locality Through CMEs and GAs., , , and . IEEE PACT, page 68-78. IEEE Computer Society, (2003)Improved spill code generation for software pipelined loops., , , and . PLDI, page 134-144. ACM, (2000)Lightning Talks of EduHPC 2022., , , , , , , , , and 16 other author(s). EduHPC@SC, page 42-49. IEEE, (2022)MIRS: Modulo Scheduling with Integrated Register Spilling., , , and . LCPC, volume 2624 of Lecture Notes in Computer Science, page 239-253. Springer, (2001)Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures., , , and . MICRO, page 237-246. ACM/IEEE Computer Society, (1998)