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Disambiguation of "Takamaeda-Yamazaki, Shinya"

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A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators.

, , , and . CANDAR, page 137-142. IEEE, (2019)

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Satoko Yamazaki

Shinya Sato

Shinya Minegishi

Noboru Yamazaki

Asuka Yamazaki

 

Other publications of authors with the same name

Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems., and . IEEE Micro, 44 (1): 38-48 (January 2024)Accelerating Decision Tree Ensemble with Guided Branch Approximation., and . HEART, page 24-32. ACM, (2022)Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations., , and . ICNC, page 343-349. IEEE Computer Society, (2012)FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects., , , , , and . FPL, page 1. IEEE, (2017)An FPGA-based scalable simulation accelerator for tile architectures., , , and . SIGARCH Comput. Archit. News, 39 (4): 38-43 (2011)QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 54 (1): 186-196 (2019)FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design., and . FPT, page 1-9. IEEE, (2022)Logarithmic Compression for Memory Footprint Reduction in Neural Network Training., , , , , , , , and . CANDAR, page 291-297. IEEE Computer Society, (2017)Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators., , , and . CANDAR, page 388-393. IEEE Computer Society, (2014)DeltaNet: Differential Binary Neural Network., , , , and . ASAP, page 39. IEEE, (2019)