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Disambiguation of "Asai, Tetsuya"

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A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators.

, , , and . CANDAR, page 137-142. IEEE, (2019)

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Kwaichiro Asai

Tetsuya Takahashi

Yusuke Asai

Tetsuya Mizutani

Tetsuya Kawata

 

Other publications of authors with the same name

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation., , , , , , , , , and 1 other author(s). ICECS, page 169-172. IEEE, (2013)Biomorphic Analog Devices based on Reaction-Diffusion Systems., and . ISMVL, page 197-206. IEEE Computer Society, (2003)Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture., , , , and . ISCAS (3), page 2535-2538. IEEE, (2005)A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology., , , and . SMC, page 6. IEEE, (2002)Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits., , and . ICONIP (1), volume 6443 of Lecture Notes in Computer Science, page 188-195. Springer, (2010)Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers., , , and . ICECS, page 140-143. IEEE, (2009)Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces., , , , , , and . ESSCIRC, page 105-108. IEEE, (2016)A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs., , , and . IEEE J. Solid State Circuits, 44 (7): 2047-2054 (2009)Towards reaction-diffusion computing devices based on minority-carrier transport in semiconductors, , and . Chaos, Solitons & Fractals, 20 (4): 863--876 (May 2004)Silicon neuron design based on phase reduction analysis., , and . SCIS&ISIS, page 1059-1062. IEEE, (2012)