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Disambiguation of "Saxena, Vishal"

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A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter.

, , , , , , , , , and . BCICTS, page 32-35. IEEE, (2018)

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Vishal Agrawal

Abhinav Saxena

Vishal Suthar

Vishal Vaibhav

Vishal Varma

 

Other publications of authors with the same name

Design and Compact Modeling of Silicon-Photonic Coupling-Based Ring Modulators for Optical Interconnects., , and . MWSCAS, page 619-622. IEEE, (2018)Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs., , and . SoCC, page 380-385. IEEE, (2011)A Deep Unsupervised Feature Learning Spiking Neural Network with Binarized Classification Layers for EMNIST Classification., , and . CoRR, (2020)Deep Convolutional Spiking Neural Networks for Image Classification., , and . CoRR, (2019)Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (2): 254-266 (2015)Hybrid CMOS-RRAM Spiking CNNs with Time-Domain Max-pooling and Integrator Re-use., , and . ISCAS, page 1828-1832. IEEE, (2022)A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh., and . ISSCC, page 222-223. IEEE, (2023)Behavioral modeling and characterization of silicon photonic Mach-Zehnder modulator., , , and . MWSCAS, page 989-992. IEEE, (2017)A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter., , , , , , , , , and . BCICTS, page 32-35. IEEE, (2018)A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (11): 1088-1092 (2015)