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Disambiguation of "Hofstra, Klaas L."

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A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.

, , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (4): 1108-1123 (2020)

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Tette Hofstra

Günther Hofstra

Elke Bettina Hofstra

Walter Klaas

Herbert Klaas

 

Other publications of authors with the same name

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET., , , , , , , , , and 20 other author(s). VLSI Circuits, page 92-. IEEE, (2019)Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms., and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 215-226. Springer, (2007)10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS., , , , , , , , , and 12 other author(s). ISSCC, page 182-183. IEEE, (2016)Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ., , , , , , , , , and 11 other author(s). CICC, page 1-8. IEEE, (2020)A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 55 (4): 1108-1123 (2020)26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology., , , , , , , , , and 7 other author(s). ISSCC, page 442-443. IEEE, (2014)