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Low power scheduling in high-level synthesis using dual-Vth library., , and . ISQED, page 507-511. IEEE, (2015)Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams., , , , , , and . ISCAS (1), page 424-427. IEEE, (2005)Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)., , and . FPGA, page 288. ACM, (2010)Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques., and . ISQED, page 297-302. IEEE, (2011)Systematic approximate logic optimization using don't care conditions., , , and . ISQED, page 419-425. IEEE, (2017)Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions., and . ATVA, volume 4762 of Lecture Notes in Computer Science, page 129-144. Springer, (2007)High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization., , and . ICRC, page 1-10. IEEE, (2018)Modular arithmetic decision procedure with auto-correction mechanism., and . HLDVT, page 138-145. IEEE Computer Society, (2009)A formal approach to debug polynomial datapath designs.. ASP-DAC, page 683-688. IEEE, (2012)Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism., , , and . VLSID, page 80-85. IEEE Computer Society, (2014)