Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.

W. Lin, H. Huang, K. Kao, M. Chiang, D. Lu, W. Hsu, Y. Wang, W. Ma, H. Tsai, Y. Lee, H. Chiang, J. Wang, and I. Radu. ESSDERC, page 9-12. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Meng Meng

Ching-Wen Hsueh

Yi-Ching Hsueh

Leo Fong-Ziang Hsueh

Chih-Jen Hsueh

Other publications of authors with the same name

6-T SRAM performance assessment with stacked silicon nanowire MOSFETs.Y. Huang, M. Chiang, W. Hsu, and S. Cheng. ISQED, page 610-614. IEEE, (2015)Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications.Y. Huang, M. Chiang, and S. Wang. ISQED, page 231-234. IEEE, (2019)Design issues and insights of multi-fin bulk silicon FinFETs.H. Li, and M. Chiang. ISQED, page 723-726. IEEE, (2012)MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.W. Lin, H. Huang, K. Kao, M. Chiang, D. Lu, W. Hsu, Y. Wang, W. Ma, H. Tsai, Y. Lee and 3 other author(s). ESSDERC, page 9-12. IEEE, (2023)Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM.J. Chen, M. Chang, S. Chen, J. Lee, and M. Chiang. ISQED, page 151-155. IEEE, (2018)Assessment of structure variation in silicon nanowire FETs and impact on SRAM.Y. Liao, M. Chiang, K. Kim, and W. Hsu. Microelectron. J., 43 (5): 300-304 (2012)How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.H. Chiang, R. Hadi, J. Wang, H. Han, J. Wu, H. Hsieh, J. Horng, W. Chou, B. Lien, C. Chang and 19 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells.M. Chang, P. Chao, and M. Chiang. ISQED, page 311. IEEE, (2021)Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes.M. Wu, and M. Chiang. ISQED, page 169-172. IEEE, (2016)An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.Y. Huang, M. Chiang, S. Wang, and S. Gupta. ICICDT, page 117-120. IEEE, (2018)

BibSonomy

Disambiguation of "Chiang, Meng-Hsueh"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.

Please choose a person to relate this publication to

Meng Meng

Ching-Wen Hsueh

Yi-Ching Hsueh

Leo Fong-Ziang Hsueh

Chih-Jen Hsueh

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chiang, Meng-Hsueh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.

Please choose a person to relate this publication to

Meng Meng

Ching-Wen Hsueh

Yi-Ching Hsueh

Leo Fong-Ziang Hsueh

Chih-Jen Hsueh

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.