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Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification.

, , , , and . ICCAD, page 241-246. IEEE Computer Society / ACM, (2003)

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Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits., , and . J. Electron. Test., 11 (3): 227-245 (1997)Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search., , , , , and . DAC, page 858-863. ACM, (2001)Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing., , and . ICCAD, page 847-854. IEEE Computer Society / ACM, (2004)An accurate model for ambiguity delay simulation., and . EURO-DAC, page 563-567. IEEE Computer Society, (1990)Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits., and . Parallel Computer Architectures, volume 732 of Lecture Notes in Computer Science, page 234-245. Springer, (1993)A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits., , and . DATE, page 78-83. IEEE Computer Society, (2002)Circuit Optimization Driven by Worst-Case Distances., and . ICCAD, page 166-169. IEEE Computer Society, (1991)Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification., , , , and . ICCAD, page 241-246. IEEE Computer Society / ACM, (2003)The Sizing Rules Method for Analog Integrated Circuit Design., , , and . ICCAD, page 343-349. IEEE Computer Society, (2001)A new power estimation technique with application to decomposition of Boolean functions for low power., , and . EURO-DAC, page 388-393. IEEE Computer Society, (1994)