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Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework., , , , , , , and . CoRR, (2020)A programmable baseband processor for massive MIMO uplink multi-user detection., , , , , and . ASICON, page 1-4. IEEE, (2015)FTDL: An FPGA-tailored Architecture for Deep Learning Systems., , , , , and . FPGA, page 320. ACM, (2020)Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers., , , , and . ICLR, OpenReview.net, (2020)Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory., , , and . FPT, page 56-63. IEEE, (2017)A Heterogeneous System for Real-Time Detection with AdaBoost., , , , , and . HPCC/SmartCity/DSS, page 839-843. IEEE Computer Society, (2016)CSB-RNN: a faster-than-realtime RNN acceleration framework with compressed structured blocks., , , , , , , , and . ICS, page 24:1-24:12. ACM, (2020)High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing., , and . J. Imaging, 5 (3): 34 (2019)The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision., , , , , and . DATE, page 1604-1609. IEEE, (2016)E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System., , , , and . DAC, page 182. ACM, (2019)