( en | de | ru )

 

Disambiguation of "Ming, Ling"

Author of the publication

copydeleteadd this publication to your clipboard
Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph.

, , , and . DATE, page 598-601. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dchi-ling Ling

Helmar Minger

Jorge Mínguez

Karl Minga

Bernhard Mingers

 

Other publications of authors with the same name

A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph., , , , and . ASICON, page 1-5. IEEE, (2013)TYMER: A Yield-based Performance Model for Timing-speculation SRAM., , , , , and . DAC, page 1-6. IEEE, (2020)A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling., , , , and . DAC, page 1-6. IEEE, (2020)An artificial neural network model of LRU-cache misses on out-of-order embedded processors., , , and . Microprocess. Microsystems, (2017)Dual fluoroscopic imaging and CT-based finite element modelling to estimate forces and stresses of grafts in anatomical single-bundle ACL reconstruction with different femoral tunnels., , , , , , and . Int. J. Comput. Assist. Radiol. Surg., 16 (3): 495-504 (2021)A Novel Delay Calibration Method Considering Interaction between Cells and Wires., , , , , , and . DATE, page 1-6. IEEE, (2023)A New Process Framework for Managing the Fuzzy Front End of New Healthcare Device Development., , , and . HCI (24), volume 14034 of Lecture Notes in Computer Science, page 480-491. Springer, (2023)A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies., , , and . ICPADS, page 267-274. IEEE, (2019)Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph., , , and . DATE, page 598-601. IEEE Computer Society, (2010)A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2197-2209 (2021)