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Disambiguation of "Miyahara, Masaya"

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A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.

, , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 422-433 (2013)

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A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers., , and . A-SSCC, page 65-68. IEEE, (2016)SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier., and . ASICON, page 24-27. IEEE, (2017)Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 476-484 (2015)SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier., and . IEICE Electron. Express, (2018)A 12-bit interpolated pipeline ADC using body voltage controlled amplifier., , and . NEWCAS, page 1-4. IEEE, (2013)A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers., , , , and . CICC, page 1-4. IEEE, (2013)20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding., , , , , , , , , and 4 other author(s). ISSCC, page 346-347. IEEE, (2014)A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier., , , and . VLSI Circuits, page 115-116. IEEE, (2018)Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector., , , , and . IEICE Trans. Electron., 102-C (7): 520-529 (2019)A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise., , and . A-SSCC, page 1-4. IEEE, (2015)