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Disambiguation of "Miyahara, Masaya"

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A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.

, , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 422-433 (2013)

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A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise., , and . A-SSCC, page 1-4. IEEE, (2015)An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 466-475 (2015)A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder., , and . ESSCIRC, page 249-252. IEEE, (2016)Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof., , , , and . ICECS, page 687-690. IEEE, (2009)A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits., , , , , and . ISSCC, page 248-249. IEEE, (2013)Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 476-484 (2015)SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier., and . IEICE Electron. Express, (2018)A 12-bit interpolated pipeline ADC using body voltage controlled amplifier., , and . NEWCAS, page 1-4. IEEE, (2013)A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers., , , , and . CICC, page 1-4. IEEE, (2013)A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers., , and . A-SSCC, page 65-68. IEEE, (2016)