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Deterministic Shift Power Reduction in Test Compression.

, , , and . VDAT, volume 711 of Communications in Computer and Information Science, page 155-167. Springer, (2017)

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Iddq Testing for High Performance CMOS - The Next Ten Years., , , , and . ED&TC, page 578-583. IEEE Computer Society, (1996)System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction)., and . Computer, 29 (11): 28-30 (1996)A Metric for Test Set Characterization and Customization Toward Fault Diagnosis., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1824-1828 (2013)Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams., , , and . DAC, page 417-420. ACM, (1991)Security vs. Test Quality: Are they mutually exclusive?. ITC, page 1414. IEEE Computer Society, (2004)Scalable Adaptive Scan (SAS)., , and . DATE, page 1476-1481. IEEE, (2009)OCI: Open Compression Interface., , , , , , , , and . ITC, page 1-4. IEEE Computer Society, (2006)Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction., , and . VTS, page 84-92. IEEE Computer Society, (2007)Fundamentals of timing information for test: How simple can we get?, , and . ITC, page 1-7. IEEE Computer Society, (2007)Integrating DFT in the Physical Synthesis Flow., , , , and . ITC, page 788-795. IEEE Computer Society, (2002)