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Disambiguation of "Usami, Kimiyoshi"

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Cache Controller Design on Ultra Low Leakage Embedded Processors.

, , , , , , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 171-182. Springer, (2009)

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Kimiyoshi Matsumura

Yukihiko Usami

 

Other publications of authors with the same name

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor., and . NVMSA, page 1-6. IEEE, (2017)An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Delay modeling and static timing analysis for MTCMOS circuits., and . ASP-DAC, page 570-575. IEEE, (2006)Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM., and . IEICE Trans. Electron., 104-C (7): 338-349 (2021)Geyser-2: The second prototype CPU with fine-grained run-time power gating., , , , , , , , , and 7 other author(s). ASP-DAC, page 87-88. IEEE, (2011)Overview on Low Power SoC Design Technology.. ASP-DAC, page 634-636. IEEE Computer Society, (2007)A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage., , , , and . IoTaIS, page 65-71. IEEE, (2023)A fine-grain dynamic sleep control scheme in MIPS R3000., , , , , , , , , and 7 other author(s). ICCD, page 612-617. IEEE Computer Society, (2008)Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs., , , , , and . NOCS, page 61-68. IEEE Computer Society, (2010)Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3482-3490 (2006)