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Geyser-2: The second prototype CPU with fine-grained run-time power gating., , , , , , , , , и 7 other автор(ы). ASP-DAC, стр. 87-88. IEEE, (2011)Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping., , , , , , , и . FPT, стр. 349-352. IEEE, (2010)Cache Controller Design on Ultra Low Leakage Embedded Processors., , , , , , и . ARCS, том 5455 из Lecture Notes in Computer Science, стр. 171-182. Springer, (2009)Cool Mega-Array: A highly energy efficient reconfigurable accelerator., , , , , , , , , и . FPT, стр. 1-8. IEEE, (2011)Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique., , , , , , , , , и 1 other автор(ы). FPT, стр. 329-332. IEEE, (2008)Power reduction techniques for Dynamically Reconfigurable Processor Arrays., , , , , , , и . FPL, стр. 305-310. IEEE, (2008)An early Holocene sea-level jump and delta initiation, и . Geophysical Research Letters, 34 (18): L18401+ (18.09.2007)A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array., , , , , и . ERSA, стр. 283-286. CSREA Press, (2009)Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors., , и . ERSA, стр. 112-118. CSREA Press, (2009)Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells., , , и . FPT, стр. 104-111. IEEE Computer Society, (2009)