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Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks.

, , , , and . J. Electron. Test., 20 (1): 25-37 (2004)

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CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits., and . ED&TC, page 266-270. IEEE Computer Society, (1997)Foreword., , and . J. Circuits Syst. Comput., 26 (8): 1702001:1-1702001:1 (2017)ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems., and . MIXDES, page 83-88. IEEE, (2020)CMOS variable-gain amplifier for low-frequency applications., , , and . DDECS, page 243-246. IEEE, (2016)Novel architecture of a digital neuron for FFNN employing special multiplication., , , , and . ECAI, volume 263 of Frontiers in Artificial Intelligence and Applications, page 933-938. IOS Press, (2014)A new efficient sorting architecture for real-time systems., and . MECO, page 1-4. IEEE, (2017)International Symposium on Design and Diagnostics of Electronic Circuits and Systems., , , , , , , , and . ITC, page 1-4. IEEE, (2019)Design of the Slope Detection Circuit for On-Chip Current Sensing., , , , and . MIXDES, page 111-115. IEEE, (2023)Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology., , , , , and . DDECS, page 1-4. IEEE, (2020)Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology., , , , and . DDECS, page 40-45. IEEE, (2016)