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Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks.

, , , , and . J. Electron. Test., 20 (1): 25-37 (2004)

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New Embedded Core Testing for System-on-Chips and System-in-Packages., and . CCECE, page 1897-1900. IEEE, (2006)Ballistic Deflection Transistors and the Emerging Nanoscale Era., , , , , and . ISCAS, page 61-64. IEEE, (2009)Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1327-1331 (2012)A Processor-In-Memory Architecture for Multimedia Compression., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (4): 478-483 (2007)1.8V 0.18µm CMOS Novel Successive Approximation ADC., , and . VLSI-SOC, page 375-379. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (7): 1411-1418 (2006)A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only)., and . FPGA, page 273. ACM, (2015)Evolutionary Cell Aided Design for Neural Network Architectures., , , and . CoRR, (2019)Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters., , and . VLSI-SOC, page 380-385. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)A C++-embedded Domain-Specific Language for programming the MORA soft processor array., , , and . ASAP, page 141-148. IEEE Computer Society, (2010)