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Disambiguation of "Arslan, Umut"

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2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.

, , , , , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)

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Umut Baysal

Umut Özsoy

Umut Aydemir

Ümüt Halik

Umut Avci

 

Other publications of authors with the same name

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines., , , , , and . CICC, page 415-418. IEEE, (2008)Efficient statistical analysis of read timing failures in SRAM circuits., , , and . ISQED, page 617-621. IEEE Computer Society, (2009)An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS., , , and . CICC, page 1-4. IEEE, (2017)2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology., , , , , , , , , and 2 other author(s). VLSIC, page 1-2. IEEE, (2014)13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology., , , , , , , , , and 2 other author(s). ISSCC, page 230-231. IEEE, (2014)A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , and 7 other author(s). ISSCC, page 212-214. IEEE, (2019)A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique., , , , , , , , , and 11 other author(s). ISSCC, page 214-216. IEEE, (2019)