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2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.

M. Meterelliyoz, F. Al amoody, U. Arslan, F. Hamzaoglu, L. Hood, M. Lal, J. Miller, A. Ramasundar, D. Soltman, I. Wan, Y. Wang, and K. Zhang. VLSIC, page 1-2. IEEE, (2014)

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Abdelhak Fatihi

Fatih Bayazit

Fatih Bilgili

Fatih Ceteci

Fatih Koyuncu

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Circuit-level techniques to control gate leakage for sub-100nm CMOS.F. Hamzaoglu, and M. Stan. ISLPED, page 60-63. ACM, (2002)Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.D. Somasekhar, B. Srinivasan, G. Pandya, F. Hamzaoglu, M. Khellah, T. Karnik, and K. Zhang. IEEE J. Solid State Circuits, 45 (4): 751-758 (2010)A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr. IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS.M. Khellah, N. Kim, J. Howard, G. Ruhl, Y. Ye, J. Tschanz, D. Somasekhar, N. Borkar, F. Hamzaoglu, G. Pandya and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. Ng, L. Wei, Y. Zhang, K. Zhang, and M. Bohr. ISSCC, page 456-457. IEEE, (2009)Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.S. Xie, C. Ni, P. Jain, F. Hamzaoglu, and J. Kulkarni. VLSI Technology and Circuits, page 112-113. IEEE, (2022)16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing.S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu, and J. Kulkarni. ISSCC, page 248-250. IEEE, (2021)An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS.A. Biswas, U. Arslan, F. Hamzaoglu, and A. Chandrakasan. CICC, page 1-4. IEEE, (2017)A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, Y. Ng, U. Bhattacharya, and K. Zhang. ISSCC, page 346-347. IEEE, (2010)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.F. Hamzaoglu, K. Zhang, Y. Wang, H. Ahn, U. Bhattacharya, Z. Chen, Y. Ng, A. Pavlov, K. Smits, and M. Bohr. ISSCC, page 376-377. IEEE, (2008)

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Disambiguation of "Hamzaoglu, Fatih"

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2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.

Please choose a person to relate this publication to

Abdelhak Fatihi

Fatih Bayazit

Fatih Bilgili

Fatih Ceteci

Fatih Koyuncu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hamzaoglu, Fatih"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.

Please choose a person to relate this publication to

Abdelhak Fatihi

Fatih Bayazit

Fatih Bilgili

Fatih Ceteci

Fatih Koyuncu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.