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Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis., , , , and . EDAC-ETC-EUROASIC, page 332-337. IEEE Computer Society, (1994)Efficient logic-level timing analysis using constraint-guided critical path search., and . IEEE Trans. Very Large Scale Integr. Syst., 4 (3): 346-355 (1996)Postroute gate sizing for crosstalk noise reduction., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1670-1677 (2004)Improved sequential ATPG using functional observation information and new justification methods., , and . ED&TC, page 262-266. IEEE Computer Society, (1995)A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification., , , , , , and . ISQED, page 232-237. IEEE Computer Society, (2004)Slope Propagation in Static Timing Analysis., , , , and . ICCAD, page 338-343. IEEE Computer Society, (2000)Static Electromigration Analysis for Signal Interconnects., , , , , and . ISQED, page 377-382. IEEE Computer Society, (2003)Driver modeling and alignment for worst-case delay noise., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (2): 157-166 (2003)Driver Modeling and Alignment for Worst-Case Delay Noise., , , , , and . DAC, page 720-725. ACM, (2001)Emerging power management tools for processor design., , , , , and . ISLPED, page 143-148. ACM, (1998)