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Algorithms for Solving Boolean Satisfiability in Combinational Circuits.

, , and . DATE, page 526-530. IEEE Computer Society / ACM, (1999)

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Efficient computation of the worst-delay corner., , and . DATE, page 1617-1622. EDA Consortium, San Jose, CA, USA, (2007)Speedpath analysis under parametric timing models., , and . DAC, page 268-273. ACM, (2010)Library Compatible Variational Delay Computation., , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 157-176. Springer, (2006)Grid-based statistical timing analysis., and . IADIS AC, page 73-80. IADIS, (2005)Effective Corner-Based Techniques for Variation-Aware IC Timing Verification., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (1): 157-162 (2010)Unifying functional and parametric timing verification.. ACM Great Lakes Symposium on VLSI, page 135-140. ACM, (2012)TAU 2013 variation aware timing analysis contest., , , , , and . ISPD, page 171-178. ACM, (2013)Handling intra-die variations in PSTA., and . ACM Great Lakes Symposium on VLSI, page 403-406. ACM, (2011)Timing analysis using propositional satisfiability., , , and . ICECS, page 95-98. IEEE, (1998)EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS., , , , , , , , , and 27 other author(s). ETS, page 1-6. IEEE, (2023)