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Improving post-silicon error detection with topological selection of trace signals.

, , , , and . VLSI-SoC, page 1-6. IEEE, (2017)

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Improving post-silicon error detection with topological selection of trace signals., , , , and . VLSI-SoC, page 1-6. IEEE, (2017)A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging., , and . IGSC, page 1-8. IEEE, (2018)Black-Hat High-Level Synthesis: Myth or Reality?, , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 913-926 (2019)COPPTCHA: COPPA Tracking by Checking Hardware-Level Activity., , , and . IEEE Trans. Inf. Forensics Secur., (2020)Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 228-251 (2021)Bottlenecks in Secure Adoption of Deep Neural Networks in Safety-Critical Applications., , and . MWSCAS, page 801-805. IEEE, (2023)Towards High-Level Synthesis of Quantum Circuits., , and . DATE, page 1-6. IEEE, (2023)Can Overclocking Detect Hardware Trojans?, , , and . ISCAS, page 1-5. IEEE, (2021)Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators., , and . ISQED, page 343-348. IEEE, (2021)RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators., , , , and . ITC, page 504-508. IEEE, (2022)