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10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS., , , и . ISSCC, стр. 1-3. IEEE, (2015)A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS., , , , , , и . ISSCC, стр. 152-154. IEEE, (2011)A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators., , , и . ISSCC, стр. 464-466. IEEE, (2012)A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS., , и . ISSCC, стр. 360-362. IEEE, (2012)A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer., , , , , , и . ISSCC, стр. 152-154. IEEE, (2012)Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells., , , , и . ICECS, стр. 494-497. IEEE, (2007)10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS., , , , и . ISSCC, стр. 192-193. IEEE, (2016)Jitter in high-speed serial and parallel links., , , , и . ISCAS (4), стр. 425-428. IEEE, (2004)A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR., , , , и . CICC, стр. 1-4. IEEE, (2018)A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter., , , , и . CICC, стр. 1-4. IEEE, (2015)