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Design considerations for low-power receiver front-end in high-speed data links., , , , and . CICC, page 1-8. IEEE, (2013)Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1818-1829 (2009)A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver., , , , , , , , , and . OFC, page 1-3. IEEE, (2019)A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS., , , , , , , , and . CICC, page 1-2. IEEE, (2021)A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO., , , , , , and . ISSCC, page 172-174. IEEE, (2019)A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B., , , , , , , and . ISSCC, page 263-272. IEEE, (2006)26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 440-441. IEEE, (2014)Strong injection locking of low-Q LC oscillators., , , , , , , and . CICC, page 699-702. IEEE, (2008)An on-die all-digital delay measurement circuit with 250fs accuracy., , and . VLSIC, page 98-99. IEEE, (2012)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)