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Disambiguation of "Flynn, Michael P."

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A "digital" 6-bit ADC in 0.25-μm CMOS.

, and . IEEE J. Solid State Circuits, 37 (3): 432-437 (2002)

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Robynne Flynn-Diez

Choi-Yeung-Chang Flynn

Sharon Flynn

Linda Jessica Flynn

Michael P Maier

 

Other publications of authors with the same name

A new transponder architecture for long-range telemetry applications., and . ECCTD, page 177-180. IEEE, (2005)A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders., , , , , and . VLSIC, page 70-71. IEEE, (2012)Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression., , , , , and . VLSIC, page 108-. IEEE, (2015)A "digital" 6-bit ADC in 0.25-μm CMOS., and . IEEE J. Solid State Circuits, 37 (3): 432-437 (2002)A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC., , , and . IEEE J. Solid State Circuits, 45 (9): 1935-1945 (2010)A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS., , , and . IEEE J. Solid State Circuits, 53 (5): 1302-1312 (2018)EP2: You're hired! The top 25 interview questions for circuit designers., and . ISSCC, page 516. IEEE, (2013)A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution., , and . ESSCIRC, page 376-379. IEEE, (2015)ADC trends and impact on SAR ADC architecture and analysis., and . CICC, page 1-8. IEEE, (2015)A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS., and . ESSCIRC, page 1-4. IEEE, (2019)