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Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications., , , и . CICC, стр. 1-4. IEEE, (2018)Research From the IEEE IBM AI Compute and Emerging Technology Symposia., , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (3): 435-438 (2019)Large-signal two-terminal device model for nanoelectronic circuit analysis., , и . IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1201-1208 (2004)A Unified Design Space for Regular Parallel Prefix Adders., и . DATE, стр. 1386-1387. IEEE Computer Society, (2004)A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)., , , , , , , и . PATMOS, том 5953 из Lecture Notes in Computer Science, стр. 307-316. Springer, (2009)Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning., , и . ISPD, стр. 29-37. ACM, (2022)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling., , , , , , , , , и 34 other автор(ы). ISSCC, стр. 144-146. IEEE, (2021)Bridging high performance and low power in processor design., , , и . ISLPED, стр. 183-188. ACM, (2014)The POWER8TM processor: Designed for big data, analytics, and cloud environments., , , , , , , , , и 10 other автор(ы). ICICDT, стр. 1-4. IEEE, (2014)Network flow based datapath bit slicing., , , , и . ISPD, стр. 139-146. ACM, (2013)