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Decomposition and technology mapping of speed-independent circuits using Boolean relations., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1221-1236 (1999)Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis., , , и . DAC, стр. 389-394. ACM Press, (1997)Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems., , , , и . DAC, стр. 110-115. ACM Press, (1999)Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications., , , и . HPEC, стр. 1-7. IEEE, (2018)High-level architectural co-simulation using Esterel and C., , , , и . CODES, стр. 189-194. ACM, (2001)What is the cost of delay insensitivity?, , , , и . ICCAD, стр. 316-323. IEEE Computer Society, (1999)Performance and energy-efficient implementation of a smart city application on FPGAs., , , , , , , , и . J. Real Time Image Process., 17 (3): 729-743 (2020)To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration., , , , , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (4): 1015-1025 (декабря 2023)Quasi-Static Scheduling of Independent Tasksfor Reactive Systems., , , , и . ICATPN, том 2360 из Lecture Notes in Computer Science, стр. 80-100. Springer, (2002)Verification and synthesis of counters based on symbolic techniques., , , и . ED&TC, стр. 176-181. IEEE Computer Society, (1997)